1. Field of the Invention
The present invention relates generally to methods for fabricating field effect transistor (FET) devices. More particularly, the present invention relates to methods for fabricating field effect transistor devices with enhanced performance.
2. Description of the Related Art
Common in the semiconductor product fabrication art is the fabrication and use of field effect transistor devices. Field effect transistor devices find use as switching devices within both semiconductor logic products and semiconductor memory products.
While field effect transistor devices are thus desirable in the semiconductor product fabrication art and essential in the semiconductor product fabrication art, field effect transistor devices are nonetheless not entirely without problems.
In that regard, as semiconductor product integration levels have increased and semiconductor device dimensions have decreased, it has become increasingly important to provide methods for fabricating field effect transistor devices with enhanced performance.
It is towards the foregoing object that the present invention is directed.
Various methods have been disclosed within the semiconductor product fabrication art for fabricating field effect transistor devices with desirable properties.
Included but not limiting among the methods are methods disclosed within: (1) Ibok, in U.S. Pat. No. 6,329,256 (a damascene method for forming a gate electrode within a field effect transistor device); and (2) Cha et al., in U.S. Pat. No. 6,348,385 (a thermal out diffusion method for forming a pair of lightly doped extension regions from a pair of doped spacer layers within a field effect transistor device).
Desirable are additional methods for fabricating within semiconductor products field effect transistor devices with enhanced performance.
It is towards the foregoing object that the present invention is directed.
A first object of the invention is to provide a method for fabricating a field effect transistor device within a semiconductor product.
A second object of the invention is to provide a method in accord with the first object of the invention, wherein the field effect transistor device is fabricated with enhanced performance.
In accord with the objects of the invention, the invention provides a method for fabricating a field effect transistor device.
To practice the method of the invention, there is first provided a semiconductor substrate having formed thereover a patterned dummy layer. There is then formed within the semiconductor substrate a pair of source/drain regions while employing the patterned dummy layer as a mask. There is then formed adjoining a pair of opposite sidewalls of the patterned dummy layer a pair of patterned sacrificial layers and stripped the patterned dummy layer from adjoining the pair of patterned sacrificial layers to provide an aperture defined by the pair of patterned sacrificial layers. There is then formed adjoining a pair of sidewalls of the aperture a pair of spacer layers and formed at the bottom of the aperture a gate dielectric layer to leave remaining a partially filled aperture. There is then formed upon the pair of patterned sacrificial layers, the pair of spacer layers and the gate dielectric layer a blanket gate electrode material layer which completely fills the aperture. There is then planarized the blanket gate electrode material layer, the pair of patterned sacrificial layers and the pair of spacer layers to form a gate electrode, a pair of planarized patterned sacrificial layers and a pair of planarized spacer layers having a pair of blunt tips. There is then stripped the pair of planarized patterned sacrificial layers and the pair of planarized spacer layers from the gate electrode. Finally, there is then implanted, while employing the gate electrode as a mask, a pair of lightly doped extension regions into the semiconductor substrate.
The invention provides a method for fabricating a field effect transistor device within a semiconductor product, wherein the field effect transistor device is fabricated with enhanced performance.
The invention realizes the foregoing object by: (1) forming within the field effect transistor device a pair of source/drain regions prior to forming a pair of lightly doped extensions regions (such that the pair of lightly doped extension regions may be formed absent exposure to a thermal annealing employed incident to forming the pair of source/drain regions); and (2) forming the pair of lightly doped extension regions while employing an ion implant method (such as to provide superior dimensional control of the location and composition of the pair of lightly doped extension regions).